Virtual to physical address translation
US5630088A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1995 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Mar 9, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed address translation look-aside buffer (TLB) for translating an explicit address, comprised of an index, a TLB index, and an offset, into a physical address. The TLB cooperates with a space register file having a plurality of space registers, each space register having an indirect address for a corresponding index value. The TLB includes a memory organized as N TLB entries, each entry having an entry space tag, a virtual tag, a valid bit, and a physical page number. A comparator is coupled to each entry which compares only the TLB index to the virtual tag. Each TLB entry further includes a matching bit memory for pre-storing the results of comparing the contents of the entry space tag with the contents (indirect address) of the space registers. The contents of the matching bit memories are then selected during the memory translation process to indicate the result of the prior comparison. The matching bit memories thus eliminate the need to access the space registers during the address translation process thereby substantially reducing the virtual-to-physical address translation time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.