Floating point exponent compare using repeated two bit compare cell
US5630160A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1995 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Mar 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnitude comparator employs plural layers of repeated circuits which are scalable to any size. The magnitude comparator indicates whether two multibit inputs are equal, and if not equal indicates if a first multibit input is greater than a second multibit input. A single bit comparator circuit receives a corresponding bit of the two multibit inputs. Each single bit comparator generates an A=B output equal to the exclusive NOR of the two inputs and an A>B output equal to the first input. The magnitude comparator includes at least one two bit comparator circuit disposed in at least one layer. Each two bit comparator circuit includes an A[0]=B[0] input, an A[0]>B[0] input, an A[1]=B[1] input and an A[1]>B[1] input. Each two bit comparator circuit generates an A=B output of an AND of signals received at the A[0]=B[0] and A[1]=B[1] inputs. Each two bit comparator circuit generates an A>B output equal to the A[1]>B[1] input if the A[0]=B[0] input is "1" and equal to the A[0]>B[0] input if the A[0]=B[0] input is "0".
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.