Method for fabricating an elevated-gate field effect transistor
US5631175A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1996 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Jan 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/221
Abstract
A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.