Method of making a semiconductor memory circuit device
US5631182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1994 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Oct 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.