Method for manufacturing capacitor of semiconductor memory device
US5631185A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1995 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Jul 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/714
Abstract
A method for manufacturing a capacitor of a semiconductor memory device is provided. A first insulating layer and a second insulating layer are formed in sequence on a semiconductor substrate on which a transistor including a source region, a drain region and a gate electrode, and a buried bit-line surrounded by insulating layer are formed. Then, a contact hole is formed by sequentially etching the layers stacked on the source region, by which the source region of the transistor is exposed, and a spacer made of an insulating substance is formed inside the contact hole, and a first conductive layer is formed on the whole surface of the resultant. Next, the first conductive layer and second insulating layer are etched, and a second conductive layer is formed on the whole surface of the resultant, and a storage electrode is formed by etching the second conductive layer using the first conductive layer as a mask. According to the method, the step for forming the contact hole is very simple and less photolithography steps are required since the first conductive layer is used as a mask for etching the second conductive layer, thereby simplifying the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.