Programmable array interconnect network
US5631578A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1995 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Jun 2, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable interconnection system for a programmable array includes pluralities of parallel buses for rows and columns of logic cells arranged in the array. Two groups of seven buses are provided for each row or column of logic cells. The buses include conductors connectable to each other, and selectively connectable to, or isolated from, the logic cells. A hierarchy of conductor lengths is disclosed to provide intra-sector and inter-sector bussing. Staggered switching is employed for adjacent sector access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.