Frequency synthesizer with adaptive loop bandwidth
US5631587A · kind A · utility
62Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1994 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Oct 11, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for a frequency synthesizer with adaptive loop bandwidth is disclosed, which is adjusted by the improved frequency synthesizer includes a phase-locked loop and a phase-locked loop adjustment circuit. The phase-locked loop has loop characteristics including a loop bandwidth, a natural frequency, a damping factor, and the like. The phase-locked loop adjustment circuit is adjusted in response to a change in output frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.