Test sequence optimization process for a circuit tester
US5631856A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1995 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Jan 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/06705
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The sequential order of movements of a number of probes within a circuit test fixture is optimized through the use of an algorithm which sequentially orders test configurations provided in an input list. Each test configuration corresponds to the locations of probes within the fixture as a particular test is performed. In a first pass of the algorithm, for each test configuration, every other test configuration is considered as a next move candidate for which a weighted distance is calculated from the test configuration. Weighting factors reflect the degree of difficulty in moving one direction instead of another. A need to move one probe before another or to move in one direction before another, in order to prevent a collision within the test fixture, is also considered. A predetermined number of next move candidates having the lowest weighted distances are placed in an intermediate list for the test configuration. In a second pass of the algorithm, test configurations are linked, one to another, to form a list reflecting a preferred order of probe movement. In the process of linking with a test configuration, the available next move candidate having the shortest weighted distance…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.