Method and apparatus for testing redundant word and bit lines in a memory array
US5631868A · kind A · utility
41Cited by
17References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 28, 1995 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Nov 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for evaluating a memory having memory elements and redundant memory elements for redundancy replacement. The redundant memory elements are tested to determine the number of good redundant memory elements. The memory elements are also tested to determine whether there are any failing memory elements. It is then determined whether a sufficient number of good redundant elements are available to replace the failing memory elements. If an insufficient number of redundant memory elements are available, the testing is stopped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.