Computer system with cascaded peripheral component interconnect (PCI) buses
US5632021A · kind A · utility
250Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1995 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Oct 25, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including primary and secondary PCI (Peripheral Component Interconnect) buses which do not "livelock". The system includes two PCI to PCI bridges between the primary and secondary buses. One of the bridges is configured to only act as a target on the primary bus and as a master on the secondary bus, the second bridge is configured to only act as master on the primary bus and as a target on the secondary bus. The determination of which data path is chosen is not made by the bridges and thus the bridges do not bias the direction of transmissions to one bus or to the other bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.