Method for preventing multi-level cache system deadlock in a multi-processor system
US5632025A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1996 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Aug 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.