Data output buffer using pass transistors biased with a reference voltage and a precharged data input
US5633603A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 1995 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Dec 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data output buffer circuit for a semiconductor device for transferring read cell data to the peripheral circuits, comprising an input terminal for inputting the read cell data, a first NMOS transistor for transferring the data from the input terminal when it has a first logic level, a first PMOS transistor for transferring the data from the input terminal when it has a second logic level, a second PMOS transistor for transferring a high logic signal in response to an output signal from the first NMOS transistor, a second NMOS transistor for transferring a low logic signal in response to an output signal from the first PMOS transistor, and an output terminal for outputting the high logic signal from the second PMOS transistor or the low logic signal from the second NMOS transistor to the peripheral circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.