Logic synthesis having two-dimensional sizing progression for selecting gates from cell libraries
US5633805A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1994 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Sep 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic synthesis method uses a two-dimensional sizing progression for selecting gates from a cell library in designing an integrated circuit. The drive load and desired performance for each logic gate in a functional configuration for the integrated circuit may be determined. The device configuration or gate to implement the logic gate may be selected from a cell library. The selected gate has a drive load range encompassing the determined drive load and achieves a desired performance target for the logic gate. A two-dimensional sizing progression may be used to help minimize layout area, power consumption, and performance loss in implementing BiNMOS gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.