Echo canceler
US5633863A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1995 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Jul 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Echo canceler. A circuit arrangement for the cancellation of echo signals, wherein in the received path, an analog/digital converter is connected with a first adder and a second adder is interposed after the analog/digital converter, with the estimated echo signal being divided into first and second portions, whereby the first portion is transmitted to the first adder and the second portion is transmitted to the second adder for the production of the received signal. In a further embodiment, a third adder is interposed between the analog/digital converter and the second adder, via which the output signal of a compensation filter is added to the signal in the received path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.