Three phase clocking for an IC shift register at the end of a long serial data path
US5633905A · kind A · utility
2Cited by
1References
3Claims
0Family size
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Key dates
| Filing date | Jun 20, 1996 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Jun 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within an integrated circuit a source of digital data is coupled to a distant destination by a serial data path that is characterized by being either an imperfect and lossy transmission line or as possessing significant high frequency attenuation. A single phase clock accompanies the data over the serial data path. A single phase to three phase clock generator at the destination creates the three phase clock. If the destination is a shift register, then the three phase clock can be used for stage-to-stage clocking within the shift register, as well as for getting data into the input bit of the shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.