Bus bridge address translator
US5634013A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1995 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | May 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer bus bridge interconnects first and second buses, the first bus being big-endian and the second bus being little-endian. First address and size signals received from the first bus during a first bus cycle are converted into second address and data unit enable signals for transmission on the second bus during a second bus cycle. The first address comprises a low-order address portion and a remaining upper-order address portion. The data unit enable signals are generated from the low-order address portion and the size signals of the first bus. An address offset is generated from the data unit enable signals. The remaining upper-order address portion of the first address are then concatenated with the address offset and a predetermined lower address portion for use as the second address. The data unit enable signals may designate, say, up to 4 possible data bytes being transferred during a single beat on the second bus. The size signals may designate, say, up to 8 possible contiguous data units being transferred during a single beat on the first bus. Here, byte enable signals are generated by first generating 8 temporary byte enable signals from the low-order address portion…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.