Method and system for efficiently fetching variable-width instructions in a data processing system having multiple prefetch units
US5634025A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 1994 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Apr 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system, a plurality of primary and secondary prefetch elements are provided for prefetching a primary portion and a secondary portion of instruction words from a group of primary and secondary memory arrays coupled to each primary and secondary prefetch element, respectively. In response to a selected primary or secondary prefetch element receiving a prefetch token, the selected primary or secondary prefetch element sequentially recalls instruction words from the group of primary or secondary memory arrays, respectively. In response to a forthcoming conditional branch instruction, a plurality of prefetch elements may initiate instruction fetching so that the proper instruction may be executed during the cycle time immediately following the conditional branch instruction. The primary prefetch elements are utilized to fetch a primary portion of a variable-width instruction word, and the secondary prefetch elements, which are synchronized with the primary prefetch elements, are utilized to fetch a secondary portion of the variable-width instruction word. Program memory space is conserved by fetching the secondary portion of an instruction word only when required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.