Integrated circuit input/output processor having improved timer capability
US5634045A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1995 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Nov 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Referring to FIGS. 1 and 2, I/O control modules (IOCMs 25-29) have channels which communicate by way of timer buses (71, 72) and pin/status buses (75-77). Channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebase values from timebase channels (80, 81) by their respective timer bus (71, 72), so there is no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). Pin/status buses (75-77) allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Pin/status buses (75-77) and timer buses (71, 72) can be independently partitioned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.