Single chip processing system utilizing general cache and microcode cache enabling simultaneous multiple functions
US5634108A · kind A · utility
15Cited by
6References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1996 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Jul 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/453
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcode cache memory is provided on a processor chip for supplying frequently used microcode instruction words to a processor. A bank of multiple Tag-Status RAMs holds addresses of microcode words residing in a bank of Data RAMs. A state machine and a special Least Recently Used Random Access Memory (LRU RAM) operate to maintain the more frequently used words in the Data RAMs so that more hits occur to provide the requested word in one clock cycle. A 90 bit microcode word with 20 fields enables the processor to perform multiple functions simultaneously in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.