High frequency transistor with reduced parasitic inductance
US5635751A · kind A · utility
20Cited by
4References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a transistor mounted on a chip substrate. A metal sheet is disposed on the metallized electrode to which the base, for example, of the transistor is electrically connected. The base is electrically connected by a wire to the metal sheet. An MOS capacitor is disposed on the metal sheet and a through-hole beneath the metal sheet connects the metallized electrode directly to a metallized ground electrode disposed on the bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.