Controllable actice terminator for a computer bus
US5635852A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 17, 1995 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Apr 17, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A controllable active terminator for a computer bus providing low power, small size, switchable termination of a computer bus having a plurality of conductors. The active terminator includes a voltage reference circuit, an enable circuit, a buffer amplifier, and a plurality of output cells. The voltage reference circuit includes a power down circuit which turns the voltage reference circuit off, using the same control signal which also disconnects the termination resistors and output transistors of the output cells. The terminator uses FET technology to produce a low-power, small size, controllable terminator having stable and reliable operating characteristics. The amplifiers used in the active terminator comprise CMOS devices and thus are relatively small and consume relatively low power. When enabled, the voltage reference circuit is used to establish a reference voltage for the linear operation of the output transistors in the output cell. The output current is supplied by terminator power. Consequently, a more reliable and stable bus termination is provided by the present active terminator which uses relatively small and low power components. The output supply current capacity…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.