Voltage controlled oscillator formed of two differential transconductors
US5635879A · kind A · utility
34Cited by
1References
8Claims
0Family size
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Key dates
| Filing date | Jun 3, 1996 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Jun 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recycling channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.