Digital read channel utilizing analog-to-digital converter with offset reduction
US5635934A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 7, 1995 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Mar 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) voltage offset (VOS) reduction circuit architecture is for use with an ADC that includes a resistive ladder network and a differential-to-single ended converter. The DC level of the single-ended output of the differential-to-single ended converter is nominally set at the mid-point of the resistive ladder network. The VOS reduction circuit includes a VOS comparator bank that receives the single-ended output, compares it with a plurality of input signals from the resistive ladder network, and provides the result of the comparison as a plurality of VOS comparator bank signals. A current digital-to-analog converter (IDAC) is coupled to receive the VOS comparator bank signals, via a latch bank, and to provide a current responsive thereto. The current from the IDAC may be provided as a trim current for adjusting the DC level of the single-ended output of the ADC differential-to-single ended converter to be closer to the mid-point of the resistive ladder network, thus reducing voltage offset caused, for example, by variations in process and temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.