Irregular pitch layout for a semiconductor memory device
US5636158A · kind A · utility
31Cited by
16References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1995 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Mar 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout arrangement for a semiconductor memory device provides additional space for locating an additional circuit device in a pitch limited circuit. A space or vacated area is created by laying out a circuit element in a manner in which the pitch of the circuit element and an adjacent circuit element is less than the pitch of two times the pitch of a connecting wire pair in a double-sided layout or less than the pitch of one connecting wire pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.