Performance of an operation on whole word operands and on operations in parallel on sub-word operands in a single processor
US5636351A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1995 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Feb 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system allows parallel data processing within a single processor. In order to allow for parallel processing of data, an arithmetic logic unit or other operation executing entity within the processing system such as a shifter is partitioned. Within each partition operations are performed on a portion of one or more operands. When the operation is to be performed on full word length operands, there is no parallel processing. Thus data is allowed to freely propagate across boundaries between the partitions. When performing the operation in parallel using a plurality of operands of less than one full word in length, data is prevented from being propagated across at least one boundary between the partitions. The principles of the present invention may also be utilized to implement a multiplier which performs parallel multiplication of partial word multiplicands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.