System and method for interfacing risc busses to peripheral circuits using another template of busses in a data communication adapter
US5636370A · kind A · utility
3Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 1995 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | May 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A conversion cache circuit, interfacing RISC busses to CISC peripheral circuits, provides master/slave Write and Read operations in a shared memory (130) and in the internal registers of the processor of said peripheral circuits (210). It enables RISC processor to Write and Read in the internal registers of the 8-bit processor in a salve operation while the 32-bit processor may perform the Write or Read operations to the shared memory through the conversion cache circuit in a master mode. The 32-bit processor may have access directly to the memory through its own direct access memory mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.