Emulator for high speed, continuous and discontinuous instruction fetches
US5636375A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1996 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Mar 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A jump judgment circuit judges whether an instruction read bus cycle of a CPU to be emulated is to be executed in a sequential order of addresses of a memory. A control circuit operates in accordance with the judgment result. Specifically, if an instruction is in the sequential order of addresses of a memory relative to the immediately preceding instruction, instruction codes previously read from the memory and converted are read from a queue and supplied to the CPU. If an instruction is not in the sequential order of addresses, which would correspond to a jump to a noncontiguous address of a memory, that instruction is read from the memory at the designated address, converted into instruction codes, and supplied to CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.