Method for interconnecting semiconductor chips in three dimensions, and component resulting therefrom
US5637536A · kind A · utility
132Cited by
25References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 13, 1995 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Apr 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01046
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and component resulting from interconnecting wafers in three dimensions, where the wafers include chips and the chips include pads. Steps in the method include connecting leads to the pads; stacking the wafers; embedding the stack by a selectively removable material; treating faces of the stack in order to reveal the leads; forming connections on the faces of the stack for interconnecting the leads; and removing the selectively removable material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.