Adjustable duty cycle clock generator
US5638016A · kind A · utility
50Cited by
8References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 18, 1995 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Apr 18, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adjustable duty cycle clock generator has first and second delay lines coupled to receive an input clock and cascaded to first and second edge detectors, respectively. The second delay line has a programmable delay and the first and second edge detectors are further coupled to set and reset inputs on an S-R latch to generate an adjustable duty cycle clock with independently adjustable high and low times proportional to the induced delays of the first and second delay lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.