Efficient architecture for correcting component mismatches and circuit nonlinearities in A/D converters
US5638071A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1996 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Jun 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.