Data communication system
US5638384A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1996 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Mar 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/33378
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In order to combine an ARQ system and an FEC system, an error correction code is inserted between an error detection code for a variable-length ARQ frame and a frame boundary flag pattern. Information to be transmitted is divided into blocks having a suitable length by a block divider in accordance with a line quality judged by a line quality judger, and then subjected to a framing operation by an information frame preparer. The information subjected to the framing operation is attached with a CRC code by a CRC code generation/application circuit, subjected by a zero insertion circuit to an insertion of a suitable number of zero bits therein to provide a distinguished frame boundary with a flag, and the transmitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.