Fast data transfer bus
US5638402A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1994 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Sep 27, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0266
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bus transceiver in a first signal processing circuit is connected to one end of a first bus connecting line for transferring a data pulse signal. A bus transceiver in a second signal processing circuit is connected to one end of a second bus connecting line for transferring a data pulse signal. Connected to the other end of the first bus connecting line is a first termination resistor. Connected to the other end of the second bus connecting line is a second termination resistor. In a portion of a predetermined length (parallel coupling portion) in the first and second bus connecting lines, the interval between the first and second bus connecting lines is held substantially constant so as to produce capacitive and inductive coupling between both the bus connecting lines. Each of the first and second bus transceivers includes a bus driver and a bus receiver. The bus receiver in the first bus transceiver generates a pulse signal substantially equal to an output pulse signal which was generated from the bus driver in the second bus transceiver, based on a pulse waveform induced in the parallel coupling portion on the first bus connecting line by the output pulse signal from the secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.