Method and system for aligning the phase of high speed clocks in telecommunications systems
US5638410A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1993 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Oct 14, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for detecting and measuring a phase difference, linearly over a range of 360.degree., between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (.o slashed.2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.