Bit-reversing method and system for linear image scaling
US5638467A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1993 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | May 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T3/4023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit-reversing method and system are disclosed for linearly scaling an image frame horizontally, vertically or both. The system includes a counter circuit for outputting the current frame-column number of the currently scanned pixel and the current frame-row number of the currently scanned frame-row. The numbers are bit reversed in a converter circuit. The bit-reversed current frame-column number is compared in a comparator circuit to a horizontal scaling constant which equals the number of pixels to be discarded in each frame-row of the image frame. The bit-reversed current frame-row number is compared in the comparator circuit to a vertical scaling constant which equals the number of frame-rows of the image frame to be discarded. If the bit-reversed current frame-row number is greater than the vertical scaling constant then the comparator circuit outputs appropriate signals to a scaling controller and an address generator for storing the currently scanned frame-row in a frame buffer. Otherwise, the comparator circuit outputs appropriate signals for discarding the currently scanned frame-row. Likewise, if the bit-reversed current column number is greater than the horizontal scali…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.