Apparatus and method for accessing SMRAM in a computer based upon a processor employing system management mode
US5638532A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1994 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Dec 6, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer systems using a processor that is capable of operating in a system management mode (SMM) employ a dedicated system management RAM (SMRAM). The processor uses the SMRAM when the processor is performing a task associated with the SMM. The processor is capable of generating a range of system addresses. The range includes a particular subrange of system addresses that are used for accessing the SMRAM. A memory controller decodes the system addresses generated by the processor and enables access to the SMRAM, regardless of whether the processor is operating in the SMM, when the controller decodes a system address of the particular subrange. The range of system addresses also includes a second subrange. The memory controller also enables access to the SMRAM when the processor is operating in the SMM and the controller decodes a system address of the second subrange. The memory controller indicates to the processor whether data associated with the enabled SMRAM can be stored in a cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.