Method and apparatus for providing data to a parallel processing array
US5638533A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 1995 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Oct 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the data values into the correct order, if necessary, and provides the retrieved data values to the processing array. The select logic and shift network preferably include arrays of multiplexers. In particular, the select logic preferably includes an array of n 2:1 multiplexers, and the shift network preferably comprises an array of n.times.n:1 multiplexers. In an alternative embodiment, the shift network includes multiple stages of arrays of multiplexers. A data register according to the present invention is particularly advantageous for video applications requiring a fast data path, where the data values are…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.