Cache memory including master and local word lines coupled to memory cells
US5640339A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1996 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Mar 11, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. A first plurality of memory cells coupled to the master word lines stores access information corresponding to a plurality of data words stored in a second plurality a memory cells coupled to a plurality of local word lines. The cache stores tag, index and Least Recently Used (LRU) information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The cache includes circuitry for efficiently updating the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.