External compensation apparatus and method for fail bit dynamic random access memory
US5640353A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1995 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Dec 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for bit defect compensation is disclosed which comprises a tag address means for storing addresses of defective bits of a DRAM; a compensation data means for storing replacing bits utilized to replace the defective bits; a control circuit that provides logic and timing controls for compensation actions; and a comparator that provides comparison function between DRAM access address and addresses stored in the tag address means, and generates a compensation address to access the replacing bits in the compensation data means when necessary. The present invention provides an improved apparatus and method for compensating for the problem of bit defect, and improving the traditional fail bit memory scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.