Semiconductor memory device and method of fabricating the same
US5640367A · kind A · utility
0Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 1996 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Feb 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.