Conversion of synchronous/asynchronous signals
US5640433A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1995 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Dec 4, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A processor controlled test set is disclosed for testing special service circuits of a telecommunication system. A microprocessor controls the overall operation of the test set, while a digital signal processor provides high speed timing signals to the various test circuits for generating the wave forms used in testing, as well as analyzes the test result signals that are converted into digital signals. A calibration of the test generator signals as well as the signal measuring path is carried out prior to the test sequence. The digital signal processor also provides gain control over a talking path to maintain stability thereof. An I/O circuit of the test set provides plural communication paths between remote equipment and the test set to initiate and carry out various tests. Processors in the I/O module are effective to convert the various protocols of the serial data, by way of software, to digital bit streams usable by the test set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.