Use of configuration registers to control access to multiple caches and nonvolatile stores
US5640530A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1995 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Feb 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for controlling data flow in a storage subsystem containing multiple cache and/or multiple NVS elements based on the operability of the cache arrays and NVS arrays. In a data processing system having a storage controller connecting a plurality of host processors and a plurality of storage devices, this invention provides a method and architecture for managing multiple storage elements within the controller, without a degradation in subsystem performance and without data integrity problems. A set of configuration registers is utilized by the microcontroller to direct cache and NVS access to the proper storage array. A configuration table is loaded with status information concerning the memory arrays at Initial Microcode Load(IML) and this information is periodically updated during controller operation. The microcode can then either directly load the entries in this table into the configuration registers or the microcode can directly reference the table to determine available resources and make the appropriate decisions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.