CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle
US5640588A · kind A · utility
65Cited by
6References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 29, 1996 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Jan 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.