Method for fabricating complementary vertical bipolar junction transistors in silicon-on-sapphire
US5641691A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1995 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | Apr 3, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
Abstract
A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.