Clock signal loss detection and recovery apparatus in multiple clock signal system
US5642069A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1994 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | Apr 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock signal failure detection and recovery circuit for use in a system utilizing multiple, redundant clock signals. Multiple clock source circuits generate a clock signal and a periodic sync pulse, which in turn are manipulated to produce a clock signal present pulse and a periodic clock pulse. The periodic clock pulse associated with one clock signal will clock the circuitry which monitors a clock signal present pulse associated with a different clock signal. In this way, the absence of a clock signal present pulse can still be clocked into the monitoring circuitry when that particular clock signal has failed. Each clock signal present pulse is compared to at least two other clock signal present pulses, and upon recognition of a predetermined number of inconsistencies between the compared clock signal present pulses, a clock signal error signal will be issued. The error signals associated with each clock signal are monitored, and selection control signals are issued to a multiplexing circuit to select specified clock signals and periodic sync pulses depending upon the state of the selection signals. The selected clock signals and periodic sync pulses become the system clock sig…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.