Method and apparatus of redundancy for non-volatile memory integrated circuits
US5642316A · kind A · utility
35Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 1996 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | May 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy circuit used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The redundancy circuit includes a redundancy predecoder circuit, a source follower EEPROM (electrically erasable programmable read only memory) memory fuse, a scheme to use the column high voltage drivers (also known as page latch) to program the EEPROM fuses, a scheme to use the regular row decoder (also known as wordline driver or x-decoder) as the redundancy row decoder, and an out-of-bound address as a redundancy enable/disable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.