Layout of semiconductor memory and content-addressable memory
US5642322A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The layout of a semiconductor memory and a content-addressable memory is adaptable for size reduction, high-speed operation and power saving. The layout of a semiconductor memory on a semiconductor chip has a plurality of memory blocks, each of which includes a plurality of memory wards, a main ward line extending from a main decoder through each memory ward, a memory block selection line extending from a subdecoder through each memory block, and a memory ward selection means provided in each memory ward of each memory block. A column of more than one row of memory cells are used to form each memory ward of each memory block, and at least one subward line for simultaneously and totally activating all the memory cells is provided for the row of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.