"Invalidation queue with ""bit-sliceability"""
US5642486A · kind A · utility
1Cited by
4References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 15, 1993 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | Jul 15, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99942
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An Invalidation Queue (IQ) arrangement in a computer system having Main Memory and, Cache-Memory, with a pair of intermediate main-buses this IQ arrangement comprising: a pair of split IQ ASIC Arrays disposed between each Cache-Memory and the main-buses and being adapted to assure identical data in all identical memory addresses in different caches, and to "remember" write-operations along the buses and to execute invalidation sequences for any Cache-Memory unit as dictated by that Cache-Memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.