Dynamic threshold voltage scheme for low voltage CMOS inverter
US5644266A · kind A · utility
74Cited by
5References
10Claims
0Family size
Inventors
Key dates
| Filing date | Nov 13, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Nov 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.