Rom encoder circuit for flash ADC'S with transistor sizing to prevent sparkle errors
US5644312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1994 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Nov 30, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A MOS ROM architecture which is fast-switching, requires almost no current under static conditions and only small current while switching, does not require a precharge mechanism and exhibits high immunity to electrical noise. A flash converter using this ROM architecture has a "one of" circuit driving a ROM encoder stage. The ROM constitutes a "one-of" to Gray- or modified Gray code encoder, or a "one-of" to binary encoder. Each bit cell in the ROM has a single NMOS transistor with its drain connected to either zero volts (representing logical 0) or to a V.sub.DD supply of, for example, 5 volts (representing logical 1). The transistor's source is connected to the bit line. All bit cell transistor gates for a given ROM address (i.e., location) are driven in parallel by an enable/disable signal. Preferably, the N-channel transistors whose drains are connected to logical 0 are about twice as large as those whose drains are connected to logical 1, to achieve desirable drain-to-source "on" resistance, R.sub.on, and obtain a "low" output voltage when sparkle codes occur. Each bit line is connected to a buffer inverter whose trigger point is scaled to operate with a bit line that can only…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.