Timing shell generation through netlist reduction
US5644498A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Jan 25, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Gate level netlists used for timing analysis in integrated circuit design are reduced using a timing shell generator while preserving critical information for timing analysis. After verification of timings, the gate level netlist is convened into a shell containing block boundary information. The function of the shell generator is to delete internal cells meeting a set of criteria. The result is a shell netlist containing a subset of the original netlist. Thus, the design cycle time involved and computing time and resources needed in ASIC development for chips using circuits represented by timing shell netlists are decreased by substituting design verification at the top level of large hierarchical netlists or large flat netlists by bottom up verification procedures using timing shells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.